1. Field of the Invention
The present invention relates to structures of static semiconductor memory devices having memory cells including MOS transistors and, more specifically to a structure of a memory cell power supply circuit for a static semiconductor memory device.
2. Description of the Background Art
FIG. 16 is a circuit diagram showing a structure of a memory cell for a static random access memory (hereinafter abbreviated as an SRAM) including a conventional MOS transistors.
Referring to FIG. 16, the conventional memory cell includes a P channel MOS load transistor P11 and an N channel MOS driver transistor N11 connected in series between power supply potentials Vcc and ground potentials GND as well as a P channel MOS load transistor P12 and an N channel MOS driver transistor N12 connected in series between power supply potentials Vcc and ground potentials GND. A connection node between P channel MOS load transistor P11 and N channel MOS driver transistor N11 is referred to as a storage node nm1, whereas a connection node between P channel MOS load transistor P12 and N channel MOS driver transistor N12 is referred to as a storage node nm2.
Transistors P11 and N11 have their gates connected to storage node nm2, and transistors P12 and N12 have their gates connected to storage node nm1.
The conventional memory cell further includes an N channel MOS access transistor Tra1 arranged between a bit line BL and storage node nm1 and having its gate potential controlled by a word line WL, and an N channel MOS access transistor Tra2 arranged between storage node nm2 and a bit line /BL and having its gate potential controlled by word line WL.
Now, each operating state of the memory cell will be described in terms of a current flowing from a memory cell power supply source, i.e., a power supply source supplying a power supply potential to sources of load PMOS transistors P11 and P12 of the memory cell.
FIG. 17 is a diagram shown in conjunction with a current flowing to all memory cells in a stand-by mode or to the memory cell in a non-selected row in a reading/writing operation mode.
In this state, N channel MOS access transistors Tra1 and Tra2 are in a cut-off state because word line WL is at an "L" level.
P channel MOS load transistor P11 on the side of storage node nm1 with "H" level data is in a conductive state, whereas N channel MOS driver transistor N11 is in the cut-off state. Thus, only a leakage current in an off state (hereinafter referred to as an off leakage current) of N channel MOS driver transistor N11 is applied from memory cell power supply source Vcc to the memory cell.
Further, N channel MOS driver transistor N12 on the side of node nm2 with "L" level data is in the conductive state, whereas P channel MOS load transistor P12 is in the cut off state. Thus, only an off leakage current of P channel MOS transistor P12 is applied from the memory cell power supply source to the memory cell.
FIG. 18 is a diagram shown in conjunction with a current flowing to a memory cell in a selected row during a reading operation as well as in a selected row and non-selected column during a writing operation.
The portion on the side of storage node nm with the "H" level data will be described.
P channel MOS load transistor P11 is in the conductive state, whereas N channel MOS driver transistor N11 is in the cut off state. Thus, only an off leakage current of N channel MOS transistor N11 is applied from the memory cell power supply source to the memory cell.
Although word line WL is at the "H" level, a gate, drain, and source of N channel MOS access transistor Tra1 are all at the "H" level as bit line BL is also precharged to the "H" level. Thus, a current is not supplied between the memory cell and bit line BL.
Next, the portion on the side of storage node nm2 with the "L" level data will be described.
N channel MOS driver transistor N12 is in the conductive state, whereas P channel MOS load transistor P12 is in the cut off state. Thus, only an off leakage current of P channel MOS load transistor P12 is applied from the memory cell power supply source to the memory cell.
As word line BL is at the "H" level and the bit line is also precharged to the "H" level, a gate and drain of N channel MOS access transistor Tra2 are both at the "H" level and a source thereof is at the "L" level. Thus, a column current Ic is supplied from bit line /BL toward storage node nm2 as indicated by an arrow in FIG. 18 and then supplied to ground GND via driver transistor Tra2.
However, a power supply potential for precharging bit line /BL to the "H" level and a power supply potential to the memory cell are supplied from separate paths, so that only the off leakage current of P channel MOS load transistor P 12 is applied from the memory cell power supply source.
FIG. 19 is a diagram shown in conjunction with a current supplied to a memory cell to be rewritten in a selected row and in a selected column during a writing operation. First, the portion on the side to be changed from the "L" level to the "H" level (on the side of storage node nm1) will be described.
P channel MOS load transistor P11, initially in the cut off state, is brought into the conductive state as the level of storage node nm2 which is connected to P channel MOS transistor P12 paired with P channel MOS load transistor P11 is changed from the "H" to "L" level.
N channel MOS driver transistor Nil, initially in the conductive state, is brought into the cut off state as the level of storage node nm2 on the side of N channel MOS driver transistor N12 paired with N channel MOS driver transistor N11 is changed from the "H" to "L" level.
As word line WL is at the "H" level and bit line BL is precharged to the "H" level, initially, a gate and drain of N channel MOS access transistor Tra1 are both at the "H" level and a source thereof is at the "L" level. Thus, a current Ic is supplied from bit line BL to storage node nm1 as indicated by an arrow shown in FIG. 19, and supplied to ground GND via a driver transistor. However, when N channel MOS driver transistor N11 is brought into the cut off state, the flow of current Ic sooner or later stops.
A power supply potential for precharging bit line BL to the "H" level and a power supply potential of the memory cell are supplied by separate paths, so that only an off leakage current of P channel MOS load transistor P11 is initially supplied from the memory cell power supply source and only an off leakage current of N channel MOS transistor N11 is supplied from the memory cell power supply source after the writing operation.
Next, the portion on the side to be written from the "H" to "L" level (on the side of storage node nm2) will be described.
P channel MOS load transistor P12 is initially in the conductive state, but brought into the cut off state as the level of storage node nm1 on the other side is changed from the "L" to "H" level.
N channel MOS driver transistor N12 is initially in the cut off state, but brought into the conductive state as the level of storage node nm1 on the other side is changed from the "L" to "H" level.
Word line WL is at the "H" level, and bit line /BL has been brought down to be "L" level by a writing driver. Thus, a gate and drain of N channel MOS access transistor Tra2 are both at the "H" level, and a source thereof is at the "L" level, so that a current Imc is supplied from the memory cell power supply source to the storage node via a load transistor and further supplied to bit line /BL as indicated by an arrow. The flow of current Imc sooner or later stops as P channel MOS load transistor P12 is brought into the cut off state.
Such a current Imc flowing from the memory cell power supply source to the memory cell is only generated for the memory cell to be rewritten in the selected row and in the selected column during the writing operation. In addition, such a significant current Imc is generated after word line WL rises and the bit line attains to the "L" level by a write driver and until the latched data of the memory cell is inverted and the writing operation is completed.
FIG. 20 is a diagram showing a relationship between a current flowing from the memory cell power supply source to the memory cell and a power supply voltage of the memory cell.
More specifically, a greater amount of current is always supplied to the memory cell from the memory cell power supply source during the writing operation than during the reading operation. In addition, as memory cell power supply voltage Vcc increases with an increase in an externally supplied power supply voltage, the current supplied from the memory cell power supply source during the writing operation more dramatically increases.
There may be an upper limit to the voltage allowing the writing operation and an operating voltage of the device is thereby disadvantageously restricted, due to a property of the memory cell.
FIG. 21 is a schematic diagram shown in conjunction with a case where an upper limit to the power supply voltage enabling the operation of the memory cell is restricted by the presence of parasitic resistance when memory cell power supply voltage Vcc is relatively high during the writing operation.
As shown in FIG. 21, when there is a high parasitic resistance Rp11 or Rp2l due to some reason, a potential at storage node nm1 or nm2 is determined by a voltage division by the resistance from memory cell power supply voltage Vcc to a ground potential.
Thus, even if the level of bit line /BL on the side rewriting to the "L" level is brought down to the "L" level, a potential at storage node nm2 cannot be brought down to a logic threshold value of an inverter including driver transistor P11 and load transistor N11 on the side of the other bit line BL. As a result, the writing operation for inverting the latched data cannot be performed. This tendency is even more significant when memory cell power supply voltage Vcc is high, which corresponds to the case where equivalent resistance of load transistor P11 or P12 is relatively small.
FIG. 22 is a diagram shown in conjunction with the case where a lower limit to an operating voltage of the device is restricted when memory cell power supply voltage Vcc is low during a reading operation.
In the reading operation, generally, the lower limit to memory cell power supply voltage Vcc of the device tends to be restricted.
FIG. 22 is a diagram shown in conjunction with an output potential with respect to an input potential of the memory cell inverter when word line WL is risen, in connection with two inverters forming a latch in the memory cell.
Each of circles in FIG. 22 is referred to as a static noise margin (SNM). The larger circle indicates that the reading operation is more stabilized.
As shown in FIG. 22, when power supply voltage Vcc is low, SNM is small. In this case, stability of the reading operation is lower than in the case where memory cell power supply voltage Vcc is high.
As described above, the upper limit of the voltage enabling operation of the device is restricted by the writing operation, and the lower limit of the range of the memory cell power supply voltage enabling operation of the device is restricted by the reading operation. As a result, in the conventional static semiconductor memory device, it is difficult to ensure a sufficient range of the operating voltage.
On the other hand, disclosed in Japanese Patent Laying-Open No. 4-132080 is a structure in which a circuit providing power supply to the memory cell is arranged between memory cell power supply Vcc and a high-resistance load memory cell in order to reduce a stand-by current of the high-resistance load memory cell.
In a circuit structure shown in FIG. 4 of the aforementioned laid-open application No. 4-132080, however, an IDSS of a memory cell power supply PMOS transistor outputting a potential to be supplied to the memory cell merely corresponds to an upper limit of a stand-by current of the memory cell array to which the memory cell power supply PMOS transistor is connected. As described above, in a full CMOS memory cell, data cannot be written to the memory cell during the writing operation with high power supply voltage Vcc because a driving force of a load PMOS is too high. The problem that the data cannot be written to the memory cell nor a solution therefor is not described in the aforementioned application.